1. Field of the Invention
The present invention relates to a comparator which can be used in solid-state imaging devices represented by CMOS image sensors, a method of calibrating the comparator, a solid-state imaging device, and a camera system.
2. Description of the Related Art
Recently, CMOS image sensors are attracting attention as solid-state imaging devices (image sensors) which can replace CCDs. The reason is as follows.
The manufacture of CCD pixels requires dedicated processes, and a plurality of power supply voltages are required to operate them. Further, the pixels must be operated in combination with a plurality of peripheral ICs.
On the contrary, various problems encountered in CCDs such as very high system complexity are overcome in CMOS image sensors.
CMOS image sensors can be manufactured using manufacturing processes similar to those used for common CMOS type integrated circuits. The sensors can be driven by a single power supply, and they may employ a single chip on which a mixture of analog circuits and logic circuits manufactured using CMOS processes is provided.
Therefore, CMOS image sensors have a plurality of significant advantages including a reduction in the number of peripheral ICs.
The main stream of CCD output circuits is one channel outputting utilizing an FD amplifier having a floating diffusion (FD).
The main stream of CMOS image sensors is column-parallel output type sensors which have an FD amplifier at each pixel and which provides an output by selecting a certain row of pixels of the pixel array and simultaneously reading the pixels in the column direction.
The reason is as follows. It is difficult to obtain sufficient driving capability with the FD amplifiers provided in the pixels, and a reduction in the data rate is therefore required. Thus, parallel processing is considered advantageous.
A wide variety of signal output circuits for such column-parallel output type CMOS image sensors have been proposed.
Techniques used for reading out a pixel signal from a CMOS image sensor include a method as follows. Signal charge to serve as an optical signal generated by a photoelectric conversion element such as a photodiode is read out after temporarily sampling the charge into a capacitance provided downstream of the element through a MOS switch disposed near the element.
In the sampling circuit, the sampling capacitance value normally has noise that is negatively correlated with the same. When signal charge is transferred from a pixel to the sampling capacitance, the signal charge is completely transferred using a potential gradient, and no noise is therefore generated in this process of sampling. However, noise is generated at the preceding step of resetting the voltage level of the capacitance to a certain reference level.
A common technique for eliminating such a noise is correlated double sampling (CDS). According to the technique, the state of signal charge immediately before sampling (reset level) is read out and stored, and the level of the signal after the sampling is read out. Then, subtraction is carried out between the levels to eliminate a noise.
There is a variety of specific methods for carrying out CDS.
A common CMOS image sensor will now be described.
FIG. 1 is a diagram showing an example of a pixel of a CMOS image sensor including four transistors.
For example, a pixel 10 includes a photodiode 11.
The pixel 10 includes four transistors as active elements associated with the single photodiode 11, i.e., a transfer transistor 12, an amplifier transistor 13, a selection transistor 14, and a reset transistor 15.
The photo diode 11 performs photoelectrical conversion of incident light into electrical charge (electrons in this case) in an amount corresponding to the quantity of the light.
The transfer transistor 12 is connected between the photodiode 11 and a floating diffusion FD. A drive signal TR is supplied to the gate (transfer gate) of the transfer transistor 12 through a transfer control line LTx to transfer the electrons obtained by photoelectric conversion at the photodiode 11 to the floating diffusion FD.
The gate of the amplifier transistor 13 is connected to the floating diffusion FD. The amplifier transistor 13 is connected to a signal line LSGN through the selection transistor 14, and the transistor forms a source follower in combination with a constant current source 16 provided outside the pixel.
An address signal SEL is supplied to the gate of the selection transistor 14 through a selection control line LSEL to turn the selection transistor 14 on.
Thus, the amplifier transistor 13 amplifies the potential of the floating diffusion FD and outputs a voltage according to the potential onto an output (vertical) signal line LSGN. A signal voltage thus output from each pixel is output to a pixel signal readout circuit through the signal line LSGN.
The reset transistor 15 is connected between a power supply line LVDD and the floating diffusion FD.
A reset signal RST is supplied to the gate of the reset transistor 15 through a reset control line LRST to reset the potential of the floating diffusion FD to the potential of the power supply line LVDD.
More specifically, the pixel is reset by turning the transfer transistor 12 on to discharge the charge accumulated in the photodiode 11 serving as a photoelectric conversion element. Then, the transfer transistor 12 is turned off, and the photodiode 11 converts an optical signal into electrical charge and accumulate the charge.
Readout is carried out as follows. The reset transistor 15 is turned on to reset the floating diffusion FD. Then, the reset transistor 15 is turned off, and the voltage at the floating diffusion FD at that time is output through the amplifier transistor 13 and the selection transistor 14. The output thus provided is referred to as “P-phase output”.
Next, the transfer transistor 12 is turned on to transfer the charge accumulated in the photodiode 11 to the floating diffusion FD, and the voltage at the floating diffusion FD at that time is output through the amplifier transistor 13. The output thus provided is referred to as “D-phase output”.
A difference between the D-phase output and the P-phase output is obtained as an image signal. Thus, the image signal can be obtained while eliminating not only variation of a DC component output from each pixel but also FD reset noise at the floating diffusion.
Those operations are simultaneously performed at pixels of each row because the gates of the transfer transistors 12, the selection transistors 14, and the reset transistors 15 are connected on a row-by-row basis.
A wide variety of circuits have been proposed as pixel signal readout (output) circuits for column-parallel output type CMOS image sensors.
One of the most advanced forms of such sensors is a type in which an analog-digital converter (hereinafter abbreviated to “ADC”) is provided at each column to obtain a pixel signal in the form of a digital signal.
For example, CMOS image sensors having such column-parallel type ADCs are disclosed in W. Yang et al., “An Integrated 800×600 CMOS Image System” ISSCC Digest of Technical Papers, pp 304-305, February 1999 (Non-Patent Document 1) and JP-A-2005-278135 (Patent Document 1).
FIG. 2 is a block diagram showing an exemplary configuration of a solid-state imaging device (CMOS image sensor) 20 having column-parallel ADCs.
As shown in FIG. 2, the solid-state imaging device 20 includes a pixel section 21, a vertical scan circuit 22, a horizontal transfer scan circuit 23, and a timing control circuit 24.
The solid-state imaging deice 20 further includes an ADC group 25, a digital analog converter (hereinafter referred to as DAC) 26, an amplifier circuit (S/A) 27, and a signal processing circuit 28.
The pixel section 21 is configured by disposing pixels including a photodiode and an in-pixel amplifier, for example, as shown in FIG. 1 in the form of a matrix.
The solid-state imaging device 20 includes control circuits disposed for sequentially reading signals from the pixel section 21, i.e., the timing control circuit 24 which generates an internal clock, the vertical scan circuit 22 which controls row addresses and row scanning, and the horizontal transfer scan circuit 23 which controls column addresses and column scanning.
The ADC group 25 is an array of a plurality of ADCs.
Each ADC includes a comparator 25-1 for performing comparison between a reference voltage Vslop that is a ramp waveform (RAMP) obtained by changing a reference voltage generated by the DAC 26 stepwise and an analog signal obtained from a pixel on each row through the vertical signal line.
Further, each ADC includes a counter 25-2 which counts the comparison time of the comparator 25-1 and a latch 25-3 which holds the result of the counting.
The ADC group 25 has a conversion function to obtain an n-bit digital signal, and one ADC is disposed on each vertical signal line (column line) to form column-parallel ADC blocks.
The output of each latch 25-3 is connected to a horizontal transfer line 29 having a width of, for example, 2n bits.
2n amplifier circuits 27 associated with the horizontal transfer line 29 and a signal processing circuit 28 are provided.
An analog signal (potential Vsl) read out onto a vertical signal line of the ADC group 25 is compared with the reference voltage Vslop (which is a sloped waveform changing with a certain gradient) by the comparator 25-1 disposed at each column.
At this time, the counter 25-2 disposed at each column similarly to the comparator 25-1 operates. The potential (analog signal) Vslop having a ramp waveform and the value of the counter undergo changes in one-to-one correspondence with each other, whereby the potential (analog signal) Vsl on the vertical signal line is converted into a digital signal.
A change in the reference voltage Vslop is converted into a change in time, and the time is counted using a certain period (clock) to convert it into a digital value.
When the analog electrical signal Vsl and the reference voltage Vslop equal to each other, the output of the comparator 25-1 is inverted to stop the clock input to the counter 25-2. Thus, A/D conversion is completed.
When the above-described A/D conversion period ends, the horizontal transfer scan circuit 23 inputs the data held in the latch 25-3 to the signal processing circuit 28 through the horizontal transfer line 29 and the amplifier circuit 27, whereby a two-dimensional image is generated.
A column-parallel output process is performed as thus described.